1. Field of the Invention
The present invention relates to a semiconductor memory and a method of manufacturing the semiconductor memory.
2. Description of the Related Art
The functional level and storage capacity of a semiconductor memory have been increased by highly integrating memory cell transistors (see, e.g., JP-A 2000-174241 (KOKAI)). This poses the problem that as the micropatterning of the gate of the memory cell transistor advances, the channel length decreases, and the short-channel effect increases.
Also, as the gate length and gate width decrease, the volume of a floating gate electrode reduces, and a threshold fluctuation when one electron accidentally leaks increases. For example, in the generation having a gate length of 20 nm, the volume of the floating gate electrode is about (20 nm)3, and the calculated threshold fluctuation when one electron leaks is about 20 mV.
In addition, the decrease in gate width weakens the control power by the gate. For example, in the generation having a gate length of 20 nm, the gate width is also about 20 nm, and this makes it difficult to close the channel by the gate.
Furthermore, when using a depletion type (D-type) transistor including a channel region, source region, and drain region having the same conductivity type in order to suppress the short-channel effect, the channel region is pinched off by a depletion layer extending from the channel region side by sandwiching the channel region between a gate insulating film and buried insulating film. When the channel region is thinned to improve the pinch-off characteristic of the D-type transistor, it is sometimes impossible to secure a sufficient contact area by which etching for forming a contact hole penetrates the buried insulating film. As a consequence, the contact resistance rises.